Many wire-line multi-channel communication systems, such as digital subscribe line (DSL) systems and gigabit/multi-gigabit Ethernet systems suffer from inter-symbol interference (ISI) and cross-talk interferences, such as echo, near-end crosstalk (NEXT), and far-end crosstalk (FEXT). Traditionally, equalization is individually performed at each channel to combat ISI, and noise cancellation technique is applied at the receiver side to mitigate the effect of echo, NEXT and FEXT interference. However, it is noticed that FEXT inherently contains information of the signals transmitted from the far end transmitters, and it is important to exploit this information in FEXT to facilitate signal recovery rather than simply cancel it as noise. Hence, a new joint equalization scheme which can efficiently deal with ISI and also make use of information in FEXT to achieve better performance is needed in a high-speed design of the multi-channel DSP transceiver.
Fully utilizing FEXT information in a high-speed design of the multi-channel DSP transceiver is not trivial. One prior art (See, Keshab K. Parhi, and Yongru Gu, “System and method for MIMO equalization for DSP transceivers”, U.S. Pat. No. 7,561,633, filed on Jul. 14, 2009) proposed to use a typical MIMO-DFE structure to jointly deal with both FEXT and ISI in 10GBASE-T (See, J. Chen, Y. Gu and K. K. Parhi, “MIMO Equalization and Cancellation for 10GBASE-T,” in Proc. of 2006 IEEE Int. Conf. on Acoustics, Speech, and Signal Processing (ICASSP), vol. 4, pp. 637-640, May 2006). Although the advantage of the MIMO equalization technique has been demonstrated, the main drawback is that the MIMO-DFE architecture suffered from the error propagation problem, which degrades system performance significantly when input SNR is very low. In addition, the feedback loops inside the MIMO-DFE architecture limit their high-speed implementation in a DSP transceiver. To eliminate the problem of error propagation in real applications, another prior art proposed to apply Tomlinson-Harashima Precoder (THP) into MIMO equalization, and simply implemented the MIMO-DFE part at the transmitter side to pre-equalize the cross-channel interferences, i.e., a straight-forward MIMO-THP equalization scheme (See, Y. Chien, Y. Tu, H. Tsao, and W. Mao, “Equalization and interference cancellation with MIMO THP for 10GBASE-T,” in 2007 IEEE Workshop on Signal Processing Systems, pp. 95-100, 2007). However, the resulting MIMO-THP architecture is not supported in the 10GBASE-T standard, where only four separate TH precoders are required at each channel. In addition, the high-speed implementation of a MIMO-TH precoder is very difficult.
To solve these problems, a new equalization scheme which combined the general MIMO equalization technique with the TH precoding technique was proposed in one of our previous inventions (See, Keshab K. Parhi, and Yongru Gu, “System and method for MIMO equalization for DSP transceivers”, U.S. Pat. No. 7,561,633, filed on Jul. 14, 2009), where the proposed method inherited the advantage of MIMO equalization and also alleviated the error propagation problem such that a better SNR performance could be achieved. In addition, the proposed architecture complied with current 10GBASE-T standard and could be applied into the real application of a 10GBASE-T DSP transceiver design. However, the partial MIMO-DFE structure used in the proposed design to combat the residual post-cursor FEXT still has cross-feedback filters, which limit their high speed implementation. Moreover, due to effect of the TH precoding, the inputs to these feedback filters are not finite numbers any more, which will further increase the hardware implementation cost.
What is needed is a new design methodology and an implementation method for efficiently dealing with both ISI and FEXT crosstalk in a multi-channel system such that the limitations of the existing schemes can be overcome and a high-speed implementation of the proposed scheme with low complexity can be achieved in a DSP transceiver design.